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Freescale Semiconductor /MK21D5WS /PTD /PDOR

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Interpret as PDOR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PDO

PDO=0

Description

Port Data Output Register

Fields

PDO

Port Data Output

0 (0): Logic level 0 is driven on pin, provided pin is configured for general-purpose output.

1 (1): Logic level 1 is driven on pin, provided pin is configured for general-purpose output.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data